Extensible Homebrew Computer Detailed System Manual

Release 0 Preliminary
By

Copyright Information

All files in this project archive (or repository) excluding documents which specifies any other license in its header or “LICENSE” file of its parent directory follow BSD-2-Clause, except for the that the font data of documentations using template which is used in this documentation: The contents of this repository do not warrant its proper operation, and does not warrant its correct documentation. Reading this document, it is recommtded to check its desired operation from code or binary files on your own.

Trademarks

License

BSD-2-Clause LICENSE
Copyright 2024 Minsu Kwon (kms1212)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Before You Read This Document...

This document is detailed system manual of the homebrew computer powered by Motorola MC68030 Microprocessor. Its coverage is from low-level hardware structures and electrical characteristics to firmware operation calls to create your own bootloader and operating system, port existing applications or operating systems to this architecture. This is an free and open computer architecture; you can freely create, modify, delete, and redistribute any contents of it without almost every limitation. To read detailed information, see the license text inside of a box in the previous page.

Contacts

You can visit https://github.com/ehbc-project/ehbc-docs to create an issue to this repository.

Related Documents

More detailed informations of each components/standard used in this architecture may be needed to comprehtd their operation, referencing documents in following table is recommded.

Title Contents
MC68030 Enhanced 32-Bit Microprocessor User's Manual Detailed description of MC68030 Microprocessor
MC68881/MC68882 Floating-Point Coprocessor User's Manual Detailed description of MC68882 Floating-point coprocessor
FLEX® 6000 PLD Family Datasheet Electrical characteristics, device architecture, timing parameters, etc. of Altera® FLEX® 6000 FPGA Family
MAX® 7000 PLD Family Datasheet Electrical characteristics, device architecture, ISP programming methods, timing parameters, etc. of Altera® MAX® 7000 CPLD Family
Altera® Configuration Handbook Configuration methods for Altera® FPGA Families.
JEDEC Standard No.21-C Page 4.4.2 Description of JEDEC 72-pin SIMM Memory module standard.
030HBC Software Development Supplement Manual Considerations and detailed information regarding software (Bootloader/OS/Application) development

Note that this list of related documents can be updated without noticing.

Table of Contents

Overview

Contents in this chapter roughly explains about the entire architecture of the `030 Extensible Homebrew Computer. The architecture of this system is designed to provide flexible operations, rich system functions, and large expansion capabilities.

Features

The features and characteristics of the `030 Extensible Homebrew Computer (hereafter 'EHBC') are listed as follows:

Chipset Description

Processor & Coprocessor

The Main Processor

The Coprocessor

Memory Subsystem

System Memory Map

FF000000
FFFFFFFF
MMIO Area
FE100000
FEFFFFFF
ISA SMEM Area
FE010000
FE0FFFFF
ISA MEM Area
FE000000
FE00FFFF
ISA I/O Area
FD000000
FDFFFFFF
Boot Firmware Area (Maximum)
FC000000
FCFFFFFF
Reserved
00000000
FBFFFFFF
System Memory
00000000
000FFFFF
Remapped Boot Firmware Area
System Memory Map

DRAM Modules

Memory-Mapped I/O

Direct Memory Access

System Controller Unit

DRAM Controller

ISA Bus Controller

High Precision Timer

Interrupt Controller

Register Description

Register 00h: CPU Configuration Register (CCR)

Default Value 82h
Operation Read / Write
7 Force CPU Clock to 8 MHz
6-4 CPU Clock
000 33.333 MHz
001 80 MHz
010 66.667 MHz
011 50 MHz
100 40 MHz
101 60 MHz
110 25 MHz
111 20 MHz
3-2 Reserved
1 Remap firmware flash area to 0x00000000-0x000FFFFF region
0 Enable CPU Burst Operation

Register 01h: Power Configuration Register (PCR)

Default Value 00h
Operation Partial Read / Partial Write
7 Power Off System (Read: '0')
0 No operation
1 Power off system immediately
6 Reset NMI Status (Read: '0')
0 No operation
1 Reset NMI raised by power switch
5-2 Reserved
1 Power Switch Operation
0 Power off system immediately without raising NMI
1 Raise NMI
0 Power Switch Status (Read Only)
0 Not pressed
1 Pressed

Register 02h: ISA Bus Controller Configuration Register (ISAR)

Default Value 00h
Operation Read / Write
7 Enable ISA Bus Controller
6 Reserved
5 8-Bit Transfer Wait States
0 5 ISACLK
1 4 ISACLK
4 16-Bit Transfer Wait States
0 2 ISACLK
1 1 ISACLK
3-2 8-Bit Transfer Command Delay
1-0 16-Bit Transfer Command Delay
00 5 ISACLK
01 2 ISACLK
10 3 ISACLK
11 4 ISACLK

Register 03h: Firmware Flash Configuration Register (FCR)

Default Value 80h
Operation Read / Write
7 Enable Flash Controller
6-3 Reserved
2-0 ROM Latency
000 8 CPU Clocks
001 1 CPU Clock
010 2 CPU Clocks
011 3 CPU Clocks
100 4 CPU Clocks
101 5 CPU Clocks
110 6 CPU Clocks
111 7 CPU Clocks

Register 07h: DRAM Configuration Register (DCR)

Default Value 00h
Operation Read / Write
7 Enable DRAM Controller
6-4 Address Mapping Mode
3 RAS to CAS Delay
0 3 CPU clocks
1 2 CPU clocks
2 Reserved
3 Write Cycle CAS Pulse Width
0 2 CPU clocks
1 1 CPU clock
0 RAS Precharge Time
0 2 CPU clocks
1 1 CPU clock

Register 08h-0Fh: DRAM Bank Address Boundary Register (ABR0-ABR7)

Default Value 00h
Operation Read / Write
7-0 Address Boundary of the Nth DRAM Bank

Register 10h-1Bh: Timer Channel Configuration Register (TCRA(TMRA, TDRA0-TDRA2)-TCRC(TMRC, TDRC0-TDRC2))

Default Value 00h
Operation Read / Write
7 Reserved
6-4 Address Mapping Mode
3 RAS to CAS Delay
0 3 CPU clocks
1 2 CPU clocks
2 Reserved
3 Write Cycle CAS Pulse Width
0 2 CPU clocks
1 1 CPU clock
0 RAS Precharge Time
0 2 CPU clocks
1 1 CPU clock

Register 20h-2Bh: IRQ Configuration Register (ICR0-ICR11)

Default Value 00h
Operation Read / Write
7 Reserved
6-4 Address Mapping Mode
3 RAS to CAS Delay
0 3 CPU clocks
1 2 CPU clocks
2 Reserved
3 Write Cycle CAS Pulse Width
0 2 CPU clocks
1 1 CPU clock
0 RAS Precharge Time
0 2 CPU clocks
1 1 CPU clock

System Bus

Bootstrap Firmware

Firmware System Calls

External Interfaces

Power Supply

Debugging Interfaces